1. Field of the Invention
The present invention relates to a power integrated circuit and to a related manufacturing process.
2. Description of the Related Art
In conventional power integrated circuit technologies, in which the power stage is preferably of the vertical DMOS type of structure, some limitations are present when these technologies are used in high-frequency applications or when the substrate includes high-voltage (e.g. &gt;300V/.mu.sec) transients. These limitations are due to the presence of high junction capacitances between the substrate and diffused and isolated regions having respectively an N-type and a P-type conductivity and including the control circuitry of the power stage. The dimensions of these junction capacitances are proportional to the dimensions of the diffused and isolated regions. When there are abrupt changes in the voltage present on the substrate these junction capacitances transmit disturbances to the control circuitry of the power stage and compromise its operation. It would therefore be necessary either to reduce drastically the dimensions of the control circuitry or provide in the substrate a low resistance through which conveying to a ground terminal a large part of the current injected capacitively from the substrate to the control circuitry.
A known technical solution for solving these problems is described in European Patent Applications 95830060.0 and 94830229.4, both of the same applicant.
The first patent application describes a process for providing a power integrated circuit including a semiconductor substrate in which is diffused a region having an N-type conductivity. The diffused region is isolated from the substrate by an implanted buried region having a P-type conductivity. Specifically, the buried region is formed implanting high-energy boron. Normally the buried region has a thickness of approximately 1 .mu.m and a distance from the integrated circuit surface dependent upon the implantation energy. For example, if the implantation energy used is around 900 kev the buried region will be at a depth of approximately 1.5 .mu.m. To connect the buried region with the integrated circuit surface there is formed through an implantation and a successive diffusion a deep region having a P-type conductivity. The deep region includes two structurally independent regions which contact laterally the buried region. The buried region and the deep region form an annular region including the diffused region. The annular region isolates the diffused region from the rest of the integrated circuit. In this solution the thickness of the diffused region is on the order of 1 .mu.m depending also on the doping of the region. But this thickness is insufficient if the diffused region must also include the control circuitry of the power stage.
The second patent application describes a process for providing a power integrated circuit including a control circuitry incorporated in first and second diffused regions having respectively an N-type conductivity and a P-type conductivity. Again in this case the first and second diffused regions are isolated from the rest of the integrated circuit through an annular region including a buried region, implanted with high energy, and a deep region. When the implantation of the buried region is performed at 900 kev the depth at which the buried region is located does not exceed 2 .mu.m. Considering that the thickness of the buried region is approximately 1 .mu.m the residual thickness towards the surface of the integrated circuit is approximately 1 .mu.m. This thickness is insufficient for providing the control circuitry of the power stage. Indeed, the thermal cycles necessary for forming the power stage cause rising of the buried region to the surface. This shortcoming could be avoided implanting the buried region at much higher energy but the entire process would be much costlier.